{"id":3300,"date":"2026-02-10T08:54:51","date_gmt":"2026-02-10T08:54:51","guid":{"rendered":"https:\/\/www.anzer-usa.com\/resources\/?p=3300"},"modified":"2026-02-10T08:55:18","modified_gmt":"2026-02-10T08:55:18","slug":"design-for-testing-dft-pcb","status":"publish","type":"post","link":"https:\/\/www.anzer-usa.com\/resources\/design-for-testing-dft-pcb\/","title":{"rendered":"Design for Testing (DFT) PCB: How to Place Test Points for ICT"},"content":{"rendered":"\n<h2 class=\"wp-block-heading\">Key Takeaways<\/h2>\n\n\n\n<ul class=\"wp-block-list\">\n<li><strong>Design for testability PCB<\/strong> practices catch 85-95% of assembly defects before boards ship to customers<\/li>\n\n\n\n<li>Test points must be 40 mils (1.0mm) minimum diameter with 50 mils (1.27mm) center-to-center spacing for reliable ICT contact<\/li>\n\n\n\n<li>Bottom-side test point placement reduces fixture cost by 40-60% compared to dual-sided testing<\/li>\n\n\n\n<li>One test point per net is the standard, but high-reliability applications need redundancy on critical signals<\/li>\n\n\n\n<li>Test point keep-out zones (20 mils from component edges) prevent pogo pin damage during probing<\/li>\n\n\n\n<li>Bed-of-nails ICT costs $3,000-8,000 for fixtures but tests boards in 30-90 seconds vs. 15-30 minutes for flying probe<\/li>\n\n\n\n<li>Proper DFT planning during layout saves $5,000-15,000 in redesigned fixtures and 2-3 weeks in production delays<\/li>\n<\/ul>\n\n\n\n<h2 class=\"wp-block-heading\">What Is Design for Testability (And Why It Matters More Than Ever)<\/h2>\n\n\n\n<p><strong>Design for testability (DFT) is the practice of designing PCBs so manufacturing defects can be detected quickly, reliably, and cost-effectively.<\/strong> Your circuit might be perfect, but if you can&#8217;t verify that every board leaving production works correctly, you&#8217;re shipping expensive problems to customers.<\/p>\n\n\n\n<p>We see the consequences at Anzer USA every week. A customer sends a batch of 500 boards for assembly. We build them perfectly &#8211; components placed correctly, solder joints meet IPC-610 Class 3 standards, visual inspection passes. But without test points, we can&#8217;t verify:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>That every passive component has the correct value<\/li>\n\n\n\n<li>That ICs are oriented correctly and making electrical contact<\/li>\n\n\n\n<li>That there are no hidden solder bridges or cold joints<\/li>\n\n\n\n<li>That power rails are isolated and voltage levels are correct<\/li>\n<\/ul>\n\n\n\n<p><strong>The result?<\/strong> Twenty boards fail at the customer&#8217;s system-level test. The failure mode? Random. Some boards work fine. Others exhibit intermittent behavior. Debugging takes three days and costs $8,000 in engineering time.<\/p>\n\n\n\n<p>That&#8217;s $8,000 to find problems that a $200 ICT test would have caught in 60 seconds per board.<\/p>\n\n\n\n<h2 class=\"wp-block-heading\">The Economics of In-Circuit Testing (ICT)<\/h2>\n\n\n\n<h3 class=\"wp-block-heading\">Why ICT Remains the Gold Standard<\/h3>\n\n\n\n<p><strong>In-Circuit Testing uses a bed-of-nails fixture to contact specific test points and verify each component independently.<\/strong> Despite predictions that boundary scan and flying probe would replace it, ICT still dominates high-volume manufacturing:<\/p>\n\n\n\n<p><strong>ICT advantages:<\/strong><\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Test speed: 30-90 seconds per board (vs. 15-30 minutes for flying probe)<\/li>\n\n\n\n<li>Repeatability: Fixture-based testing eliminates probe positioning variance<\/li>\n\n\n\n<li>Fault coverage: Detects 85-95% of assembly defects<\/li>\n\n\n\n<li>Cost per test: $0.50-2.00 per board at volume (vs. $8-15 for flying probe)<\/li>\n<\/ul>\n\n\n\n<p><strong>ICT disadvantages:<\/strong><\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Fixture cost: $3,000-8,000 for custom bed-of-nails fixtures<\/li>\n\n\n\n<li>Test point requirement: Needs accessible test points on nearly every net<\/li>\n\n\n\n<li>Design constraints: Test points consume board real estate<\/li>\n\n\n\n<li>Fixture lead time: 2-3 weeks for fixture fabrication<\/li>\n<\/ul>\n\n\n\n<h3 class=\"wp-block-heading\">When ICT Makes Financial Sense<\/h3>\n\n\n\n<p><strong>Calculate your break-even point:<\/strong><\/p>\n\n\n\n<p>If your production volume exceeds 100-150 boards, ICT typically pays for itself:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>ICT fixture cost: $5,000 (one-time)<\/li>\n\n\n\n<li>ICT test time: 60 seconds per board<\/li>\n\n\n\n<li>Flying probe cost: No fixture, but 20 minutes per board @ $90\/hour = $30 per board<\/li>\n<\/ul>\n\n\n\n<p><strong>At 200 boards:<\/strong><\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>ICT total cost: $5,000 fixture + (200 \u00d7 $1.50) = $5,300<\/li>\n\n\n\n<li>Flying probe total cost: 200 \u00d7 $30 = $6,000<\/li>\n<\/ul>\n\n\n\n<p>At 500 boards, ICT saves $10,000. At 1,000 boards, it saves $25,000.<\/p>\n\n\n\n<p><strong>For prototypes and low-volume builds (&lt;50 boards), flying probe makes sense.<\/strong> For production runs, <strong>design for testability PCB<\/strong> principles that enable ICT are essential.<\/p>\n\n\n\n<h2 class=\"wp-block-heading\">Test Point Fundamentals: Size and Spacing Requirements<\/h2>\n\n\n\n<h3 class=\"wp-block-heading\">Minimum Dimensions for Reliable Contact<\/h3>\n\n\n\n<p><strong>Pogo pins used in ICT fixtures require specific test point geometry:<\/strong><\/p>\n\n\n\n<p><strong>Standard specifications:<\/strong><\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Minimum diameter: 40 mils (1.0mm)<\/li>\n\n\n\n<li>Recommended diameter: 50 mils (1.27mm) for improved reliability<\/li>\n\n\n\n<li>Large test points (for power\/ground): 60-80 mils (1.5-2.0mm)<\/li>\n<\/ul>\n\n\n\n<p><strong>Why size matters:<\/strong> Pogo pins have a contact tip diameter of 0.7-0.9mm. A 40-mil (1.0mm) test point provides adequate target area accounting for fixture positioning tolerance (\u00b10.1mm) and PCB registration variance (\u00b10.05mm).<\/p>\n\n\n\n<p><strong>Test points smaller than 40 mils create problems:<\/strong><\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Pogo pins miss the pad entirely (false failures)<\/li>\n\n\n\n<li>Partial contact creates intermittent connections<\/li>\n\n\n\n<li>Pin tips damage solder mask around small pads<\/li>\n\n\n\n<li>Fixture calibration becomes unreliable<\/li>\n<\/ul>\n\n\n\n<p>We&#8217;ve tested boards with 25-mil test points. Contact reliability dropped to 60-70%. Every third board showed false failures that required manual retesting.<\/p>\n\n\n\n<h3 class=\"wp-block-heading\">Center-to-Center Spacing Rules<\/h3>\n\n\n\n<p><strong>Pogo pins need physical clearance to avoid interference:<\/strong><\/p>\n\n\n\n<p><strong>IPC-9252 specifications:<\/strong><\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Minimum spacing: 50 mils (1.27mm) center-to-center<\/li>\n\n\n\n<li>Recommended spacing: 75-100 mils (1.9-2.54mm) for standard-density boards<\/li>\n\n\n\n<li>High-density spacing: 50 mils acceptable but requires premium fixture fabrication<\/li>\n<\/ul>\n\n\n\n<p><strong>The mechanical reality:<\/strong> Pogo pins mount in fixture plates with housing diameters of 1.5-2.0mm. Pins spaced at 50-mil centers require precision-drilled fixture plates and add $500-1,000 to fixture cost.<\/p>\n\n\n\n<p>Spacing test points at 100-mil centers (0.1&#8243; grid) uses standard fixture components and reduces cost by 30-40%.<\/p>\n\n\n\n<h3 class=\"wp-block-heading\">Keep-Out Zone Requirements<\/h3>\n\n\n\n<p><strong>Test points need clearance from components and board features:<\/strong><\/p>\n\n\n\n<p><strong>Minimum keep-out distances:<\/strong><\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>20 mils (0.5mm) from component bodies (prevents pogo pin collision)<\/li>\n\n\n\n<li>30 mils (0.75mm) from tall components (>5mm height)<\/li>\n\n\n\n<li>40 mils (1.0mm) from board edges (fixture frame clearance)<\/li>\n\n\n\n<li>100 mils (2.54mm) from tooling holes (fixture alignment pins)<\/li>\n<\/ul>\n\n\n\n<p><strong>Why keep-outs matter:<\/strong> ICT fixtures compress spring-loaded pogo pins with 50-150 grams of force per pin. If a pin contacts a component body instead of the test point, it either:<\/p>\n\n\n\n<ol class=\"wp-block-list\">\n<li>Damages the component (cracks ceramic capacitors, dents ICs)<\/li>\n\n\n\n<li>Deflects and misses the test point (false failure)<\/li>\n\n\n\n<li>Creates fixture wear that degrades over time<\/li>\n<\/ol>\n\n\n\n<p>Place a test point 15 mils from a 0805 capacitor, and the pogo pin will hit the capacitor 30% of the time due to normal fixture tolerances.<\/p>\n\n\n\n<h2 class=\"wp-block-heading\">Strategic Test Point Placement: Where to Put Them<\/h2>\n\n\n\n<h3 class=\"wp-block-heading\">One Test Point Per Net (With Exceptions)<\/h3>\n\n\n\n<p><strong>The standard DFT rule: Every electrical net needs at least one accessible test point.<\/strong><\/p>\n\n\n\n<p>This enables ICT to verify:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Component presence and value (resistors, capacitors, inductors)<\/li>\n\n\n\n<li>IC pin connectivity (shorts, opens, incorrect parts)<\/li>\n\n\n\n<li>Solder joint quality (cold joints, insufficient solder)<\/li>\n\n\n\n<li>Power rail integrity (shorts between VCC and GND)<\/li>\n<\/ul>\n\n\n\n<p><strong>Exceptions where multiple test points per net make sense:<\/strong><\/p>\n\n\n\n<p><strong>Power and ground nets:<\/strong> Add test points at multiple locations to verify voltage distribution. A board with five ICs should have 3-4 VCC test points to catch voltage drop issues.<\/p>\n\n\n\n<p><strong>High-reliability signals:<\/strong> Critical nets in aerospace or medical devices benefit from redundant test points. If one is blocked by a rework component, you still have access.<\/p>\n\n\n\n<p><strong>Kelvin (4-wire) resistance measurements:<\/strong> Precision current-sense resistors need two test points (force and sense) for accurate measurement.<\/p>\n\n\n\n<p><strong>Long traces:<\/strong> Nets spanning &gt;6 inches benefit from multiple test points to detect trace breaks.<\/p>\n\n\n\n<h3 class=\"wp-block-heading\">Top Side vs. Bottom Side: The Cost Trade-Off<\/h3>\n\n\n\n<p><strong>Test point location dramatically affects fixture cost and complexity:<\/strong><\/p>\n\n\n\n<p><strong>Bottom-side testing (preferred):<\/strong><\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Fixture cost: $3,000-5,000 for single-sided<\/li>\n\n\n\n<li>Test access: Probes contact bare PCB from below<\/li>\n\n\n\n<li>Design constraint: Test points must be on bottom layer, accessible from below<\/li>\n\n\n\n<li>Typical approach: 90%+ of boards use bottom-side testing<\/li>\n<\/ul>\n\n\n\n<p><strong>Top-side testing (rare):<\/strong><\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Fixture cost: $6,000-10,000 for single-sided top access<\/li>\n\n\n\n<li>Challenge: Components block probe access<\/li>\n\n\n\n<li>Use case: Only when bottom side is completely inaccessible (double-sided assembly)<\/li>\n<\/ul>\n\n\n\n<p><strong>Dual-sided testing (expensive):<\/strong><\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Fixture cost: $8,000-15,000<\/li>\n\n\n\n<li>Complexity: Requires precise board alignment and two fixture halves<\/li>\n\n\n\n<li>Use case: High-density boards where bottom-side space is exhausted<\/li>\n<\/ul>\n\n\n\n<p><strong>Design for testability PCB best practice:<\/strong> Place components on the top side and route test points to the bottom side. This allows standard, low-cost bed-of-nails fixtures.<\/p>\n\n\n\n<h3 class=\"wp-block-heading\">Critical Nets That Always Need Test Points<\/h3>\n\n\n\n<p><strong>Prioritize test access for nets most likely to fail:<\/strong><\/p>\n\n\n\n<p><strong>Power rails (VCC, GND, regulated voltages):<\/strong><\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Test for shorts between power and ground<\/li>\n\n\n\n<li>Verify voltage regulator output levels<\/li>\n\n\n\n<li>Check for solder bridges on power pins<\/li>\n<\/ul>\n\n\n\n<p><strong>IC power pins:<\/strong><\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Test point on VCC and GND for every IC (minimum)<\/li>\n\n\n\n<li>Detects reversed ICs, lifted pins, cold solder joints<\/li>\n\n\n\n<li>Enables powered ICT (in-circuit test with board energized)<\/li>\n<\/ul>\n\n\n\n<p><strong>Reset and clock signals:<\/strong><\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Verify clock oscillators are functioning<\/li>\n\n\n\n<li>Check reset circuit operation<\/li>\n\n\n\n<li>Detect trace breaks on critical timing signals<\/li>\n<\/ul>\n\n\n\n<p><strong>Analog signals at ADC\/DAC inputs:<\/strong><\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Measure reference voltages<\/li>\n\n\n\n<li>Verify signal conditioning circuits<\/li>\n\n\n\n<li>Check for incorrect resistor\/capacitor values<\/li>\n<\/ul>\n\n\n\n<p><strong>Communication interfaces (I2C, SPI, UART):<\/strong><\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Test pull-up resistors on I2C lines<\/li>\n\n\n\n<li>Verify SPI chip-select routing<\/li>\n\n\n\n<li>Detect opens on serial communication traces<\/li>\n<\/ul>\n\n\n\n<p><strong>Component-side connections:<\/strong><\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Test points on both sides of zero-ohm resistors (verifies installation)<\/li>\n\n\n\n<li>Access to both sides of series resistors (enables resistance measurement)<\/li>\n\n\n\n<li>Probe points on input and output of active filters<\/li>\n<\/ul>\n\n\n\n<h2 class=\"wp-block-heading\">Test Point Design Standards and Best Practices<\/h2>\n\n\n\n<h3 class=\"wp-block-heading\">Solder Mask Definition<\/h3>\n\n\n\n<p><strong>Test points need exposed copper for pogo pin contact, but solder mask design affects reliability:<\/strong><\/p>\n\n\n\n<p><strong>Standard test point construction:<\/strong><\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Bare copper pad (no solder mask)<\/li>\n\n\n\n<li>ENIG, HASL, or immersion silver surface finish<\/li>\n\n\n\n<li>Solder mask clearance: 5-8 mils beyond pad edge<\/li>\n<\/ul>\n\n\n\n<p><strong>Solder mask-defined vs. copper-defined:<\/strong><\/p>\n\n\n\n<p><strong>Solder mask-defined (recommended):<\/strong> Solder mask opening controls final pad size. Easier to fabricate, better registration tolerance.<\/p>\n\n\n\n<p><strong>Copper-defined:<\/strong> Copper trace defines pad size with solder mask pulled back 3-4 mils. Use only when solder mask registration is unreliable.<\/p>\n\n\n\n<h3 class=\"wp-block-heading\">Surface Finish for Test Points<\/h3>\n\n\n\n<p><strong>Different surface finishes affect pogo pin contact reliability over time:<\/strong><\/p>\n\n\n\n<p><strong>ENIG (Electroless Nickel Immersion Gold):<\/strong><\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Best choice for test points<\/li>\n\n\n\n<li>Hard nickel surface resists wear from repeated pogo pin contact<\/li>\n\n\n\n<li>Gold surface prevents oxidation<\/li>\n\n\n\n<li>Maintains low contact resistance over 10,000+ cycles<\/li>\n<\/ul>\n\n\n\n<p><strong>HASL (Hot Air Solder Leveling):<\/strong><\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Acceptable but not ideal<\/li>\n\n\n\n<li>Soft solder surface wears after 1,000-2,000 test cycles<\/li>\n\n\n\n<li>Oxidation can increase contact resistance<\/li>\n\n\n\n<li>Works fine for low-volume or prototype builds<\/li>\n<\/ul>\n\n\n\n<p><strong>Immersion Silver:<\/strong><\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Good electrical properties initially<\/li>\n\n\n\n<li>Tarnishes over time (increases contact resistance)<\/li>\n\n\n\n<li>Requires cleaning after storage >6 months<\/li>\n\n\n\n<li>Not recommended for high-volume production<\/li>\n<\/ul>\n\n\n\n<p><strong>OSP (Organic Solderability Preservative):<\/strong><\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Worst choice for test points<\/li>\n\n\n\n<li>Protective coating blocks electrical contact<\/li>\n\n\n\n<li>Must be removed before testing (defeats the purpose)<\/li>\n\n\n\n<li>Avoid OSP on test point pads<\/li>\n<\/ul>\n\n\n\n<p>If your board uses OSP or HASL for cost reasons, specify ENIG on test points only. Most fabricators support selective surface finishes.<\/p>\n\n\n\n<h3 class=\"wp-block-heading\">Via-in-Pad Test Points (When Space Is Limited)<\/h3>\n\n\n\n<p><strong>Ultra-dense designs sometimes require test points to double as vias:<\/strong><\/p>\n\n\n\n<p><strong>Via-in-pad test point design:<\/strong><\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Via diameter: 10-12 mils (0.25-0.30mm)<\/li>\n\n\n\n<li>Pad diameter: 40 mils minimum (via centered in pad)<\/li>\n\n\n\n<li>Via fill: Must be filled and plated over (VIPPO process)<\/li>\n\n\n\n<li>Surface finish: ENIG recommended<\/li>\n<\/ul>\n\n\n\n<p><strong>Cost impact:<\/strong> Via-filled and plated-over pads add $0.50-1.50 per square foot to PCB fabrication cost.<\/p>\n\n\n\n<p><strong>Contact reliability:<\/strong> Filled vias provide 90-95% of the reliability of solid test points. Acceptable for most applications, but avoid for high-reliability aerospace or medical.<\/p>\n\n\n\n<p>We&#8217;ve tested hundreds of boards with via-in-pad test points. Contact reliability is excellent if vias are properly filled. Unfilled vias create divots that pogo pins can miss, causing 15-20% false failure rates.<\/p>\n\n\n\n<h2 class=\"wp-block-heading\">Designing Test Point Layout for Efficient Fixturing<\/h2>\n\n\n\n<h3 class=\"wp-block-heading\">Grid Alignment for Cost Reduction<\/h3>\n\n\n\n<p><strong>Test points aligned to a regular grid reduce fixture cost by 25-40%:<\/strong><\/p>\n\n\n\n<p><strong>Standard grid spacing:<\/strong><\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>100-mil (2.54mm) grid: Industry standard, lowest fixture cost<\/li>\n\n\n\n<li>50-mil (1.27mm) grid: Acceptable for high-density, adds 20% to fixture cost<\/li>\n\n\n\n<li>Off-grid placement: Requires custom-drilled fixture, adds 40-60% to cost<\/li>\n<\/ul>\n\n\n\n<p><strong>Why grid alignment matters:<\/strong> Fixture fabricators stock pre-drilled plates with holes on 100-mil centers. If your test points align to this grid, fixture assembly is simple:<\/p>\n\n\n\n<ol class=\"wp-block-list\">\n<li>Select pre-drilled plate<\/li>\n\n\n\n<li>Install pogo pins at required locations<\/li>\n\n\n\n<li>Assemble fixture frame<\/li>\n<\/ol>\n\n\n\n<p>Off-grid test points require custom CNC drilling, additional alignment verification, and precision fixturing components.<\/p>\n\n\n\n<h3 class=\"wp-block-heading\">Grouping Test Points by Function<\/h3>\n\n\n\n<p><strong>Organize test points to simplify test program development:<\/strong><\/p>\n\n\n\n<p><strong>Logical grouping strategies:<\/strong><\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Power\/ground test points in one zone (enables quick power-up tests)<\/li>\n\n\n\n<li>Analog signals grouped separately from digital (different measurement techniques)<\/li>\n\n\n\n<li>IC test points clustered near the component (easier debugging)<\/li>\n\n\n\n<li>Communication bus signals grouped together (I2C, SPI, CAN)<\/li>\n<\/ul>\n\n\n\n<p><strong>Testing efficiency benefit:<\/strong> Grouped test points allow parallel testing. Your test program can measure all resistors simultaneously, then all capacitors, then all ICs. This reduces test time from 90 seconds to 45 seconds per board.<\/p>\n\n\n\n<h3 class=\"wp-block-heading\">Avoiding Test Point Shadowing<\/h3>\n\n\n\n<p><strong>Component placement can block pogo pin access even when test points are correctly sized:<\/strong><\/p>\n\n\n\n<p><strong>Shadowing occurs when:<\/strong><\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Tall components (>8mm) are within 2mm of test points<\/li>\n\n\n\n<li>Wide components overhang test point areas<\/li>\n\n\n\n<li>Through-hole parts on top side block bottom-side test points<\/li>\n\n\n\n<li>Connectors extend beyond board edge near test points<\/li>\n<\/ul>\n\n\n\n<p><strong>Prevention strategies:<\/strong><\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Move test points 5mm away from tall components<\/li>\n\n\n\n<li>Route test points to open areas between component clusters<\/li>\n\n\n\n<li>Avoid test points directly under through-hole component bodies<\/li>\n\n\n\n<li>Check 3D clearance in your CAD tool (most have DFT checkers)<\/li>\n<\/ul>\n\n\n\n<p>We&#8217;ve built ICT fixtures where 8-12 test points were completely blocked by component bodies. The fixture worked, but those nets couldn&#8217;t be tested. We had to run supplemental flying probe testing on the blocked nets, adding $4-6 per board in test cost.<\/p>\n\n\n\n<h2 class=\"wp-block-heading\">Advanced DFT Techniques for Complex Boards<\/h2>\n\n\n\n<h3 class=\"wp-block-heading\">Powered vs. Unpowered ICT<\/h3>\n\n\n\n<p><strong>Most ICT is unpowered &#8211; the fixture applies test signals without energizing the board.<\/strong> But complex boards benefit from powered testing:<\/p>\n\n\n\n<p><strong>Unpowered ICT (standard):<\/strong><\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Tests passive components (R, L, C)<\/li>\n\n\n\n<li>Tests for shorts and opens<\/li>\n\n\n\n<li>Verifies IC pin connectivity<\/li>\n\n\n\n<li>Cannot test IC functionality<\/li>\n<\/ul>\n\n\n\n<p><strong>Powered ICT (advanced):<\/strong><\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Applies power to the board during testing<\/li>\n\n\n\n<li>Tests active components (ICs, regulators, oscillators)<\/li>\n\n\n\n<li>Verifies functional operation<\/li>\n\n\n\n<li>Requires additional test points for power distribution<\/li>\n<\/ul>\n\n\n\n<p><strong>Design requirements for powered ICT:<\/strong><\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Test points on all power rails (input and output voltages)<\/li>\n\n\n\n<li>Current limit circuits to protect test equipment<\/li>\n\n\n\n<li>Isolation from external circuits (connectors, communication ports)<\/li>\n\n\n\n<li>Access to enable\/disable pins for controlled power-up<\/li>\n<\/ul>\n\n\n\n<p>Powered ICT adds $1,500-3,000 to fixture cost but catches functional failures that unpowered testing misses. For complex boards (microcontrollers, FPGAs, mixed-signal designs), the investment pays off.<\/p>\n\n\n\n<h3 class=\"wp-block-heading\">Boundary Scan (JTAG) Integration<\/h3>\n\n\n\n<p><strong>Boundary scan testing complements ICT by testing internal IC connections:<\/strong><\/p>\n\n\n\n<p><strong>IEEE 1149.1 (JTAG) provides:<\/strong><\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Access to IC pin states without physical test points<\/li>\n\n\n\n<li>Interconnect testing between boundary scan devices<\/li>\n\n\n\n<li>Flash programming for microcontrollers<\/li>\n\n\n\n<li>Reduced test point count on high-density boards<\/li>\n<\/ul>\n\n\n\n<p><strong>Design for testability PCB with boundary scan:<\/strong><\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>JTAG test points (TDI, TDO, TCK, TMS) required<\/li>\n\n\n\n<li>Daisy-chain JTAG between all compatible ICs<\/li>\n\n\n\n<li>Pull-up\/pull-down resistors on JTAG signals<\/li>\n\n\n\n<li>Access to TRST (test reset) signal<\/li>\n<\/ul>\n\n\n\n<p><strong>Hybrid testing approach:<\/strong> Use ICT for passive components and power rails, use boundary scan for digital IC interconnects. This reduces test point count by 30-50% on dense boards.<\/p>\n\n\n\n<h3 class=\"wp-block-heading\">Test Point Documentation<\/h3>\n\n\n\n<p><strong>Your manufacturing partner needs complete test point information:<\/strong><\/p>\n\n\n\n<p><strong>Essential documentation:<\/strong><\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Test point coordinate file (X\/Y locations, net names)<\/li>\n\n\n\n<li>Test point diameter and surface finish specification<\/li>\n\n\n\n<li>Net list with component values<\/li>\n\n\n\n<li>Expected test results (voltage levels, resistance ranges)<\/li>\n\n\n\n<li>Special test requirements (powered vs. unpowered, boundary scan)<\/li>\n<\/ul>\n\n\n\n<p><strong>File format:<\/strong> Export from your CAD tool in CSV or IPC-D-356 format:<\/p>\n\n\n\n<pre class=\"wp-block-code\"><code>Test Point, Net Name, X, Y, Side, Diameter\nTP1, VCC_3V3, 2.500, 3.750, Bottom, 50mil\nTP2, GND, 2.600, 3.750, Bottom, 50mil\nTP3, RESET_N, 3.200, 4.100, Bottom, 40mil<\/code><\/pre>\n\n\n\n<p><strong>This file enables:<\/strong><\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Automated fixture design (CAM software imports coordinates)<\/li>\n\n\n\n<li>Test program generation (maps nets to expected values)<\/li>\n\n\n\n<li>Fixture verification (confirms all test points are accessible)<\/li>\n<\/ul>\n\n\n\n<p>We receive 30% of designs without test point documentation. This adds 4-8 hours to fixture design as we manually extract coordinates from Gerber files.<\/p>\n\n\n\n<h2 class=\"wp-block-heading\">Common DFT Mistakes (And How to Avoid Them)<\/h2>\n\n\n\n<h3 class=\"wp-block-heading\">Mistake #1: No Test Points on Dense Boards<\/h3>\n\n\n\n<p><strong>Engineers assume &#8220;flying probe will handle it&#8221; and skip test point planning.<\/strong><\/p>\n\n\n\n<p><strong>Reality:<\/strong> Flying probe costs $25-40 per board and takes 20-30 minutes. At 500 boards, that&#8217;s $12,500-20,000 vs. $5,500 for ICT.<\/p>\n\n\n\n<p><strong>Solution:<\/strong> Allocate 2-3% of board area for test points during initial layout. A 4&#8243; \u00d7 6&#8243; board has 24 square inches of area. Reserve 0.5 square inches for test access.<\/p>\n\n\n\n<h3 class=\"wp-block-heading\">Mistake #2: Test Points on Top Side Only<\/h3>\n\n\n\n<p><strong>Placing test points on the component side forces expensive top-side fixtures or dual-sided testing.<\/strong><\/p>\n\n\n\n<p><strong>Reality:<\/strong> Top-side ICT fixtures cost 60-80% more than bottom-side fixtures. Components block probe access, reducing fault coverage.<\/p>\n\n\n\n<p><strong>Solution:<\/strong> Default to bottom-side test points. Use vias to route critical top-side signals to bottom-side test points.<\/p>\n\n\n\n<h3 class=\"wp-block-heading\">Mistake #3: Undersized or Improperly Spaced Test Points<\/h3>\n\n\n\n<p><strong>40-mil diameter and 50-mil spacing are minimums, not recommendations.<\/strong><\/p>\n\n\n\n<p><strong>Reality:<\/strong> Fixture tolerances and PCB registration variance mean 40-mil test points have 5-10% contact failures. 50-mil test points improve reliability to 98-99%.<\/p>\n\n\n\n<p><strong>Solution:<\/strong> Use 50-mil diameter as your standard. Only drop to 40-mil when space is absolutely constrained.<\/p>\n\n\n\n<h3 class=\"wp-block-heading\">Mistake #4: Test Points Under Components<\/h3>\n\n\n\n<p><strong>Test points routed under IC packages or connectors are inaccessible to pogo pins.<\/strong><\/p>\n\n\n\n<p><strong>Reality:<\/strong> Fixture can&#8217;t probe through component bodies. We&#8217;ve seen 20-30 test points blocked by poor placement.<\/p>\n\n\n\n<p><strong>Solution:<\/strong> Run DFT clearance checks in your CAD tool. Flag any test point within 2mm of component bodies.<\/p>\n\n\n\n<h3 class=\"wp-block-heading\">Mistake #5: Forgetting Test Points on Power Rails<\/h3>\n\n\n\n<p><strong>Designers add test points to signal nets but forget VCC and GND.<\/strong><\/p>\n\n\n\n<p><strong>Reality:<\/strong> Power rail shorts are the #1 cause of board failure (30-40% of defects). Without test access, you can&#8217;t detect them until functional test.<\/p>\n\n\n\n<p><strong>Solution:<\/strong> Minimum of two test points per power rail (VCC and GND). Add more for boards with multiple power domains or distributed loads.<\/p>\n\n\n\n<h3 class=\"wp-block-heading\">Mistake #6: No Test Strategy Discussion During Design Review<\/h3>\n\n\n\n<p><strong>Test point placement happens at the end of layout as an afterthought.<\/strong><\/p>\n\n\n\n<p><strong>Reality:<\/strong> Retrofitting test points into a finished layout forces compromises. Test points end up in suboptimal locations or get omitted.<\/p>\n\n\n\n<p><strong>Solution:<\/strong> Include DFT review at 50% layout completion. Lock test point locations before final routing.<\/p>\n\n\n\n<h2 class=\"wp-block-heading\">Real-World DFT Case Study: Medical Device Controller<\/h2>\n\n\n\n<p>A medical device manufacturer approached Anzer USA with a patient monitoring system controller board:<\/p>\n\n\n\n<p><strong>Initial design:<\/strong><\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>6-layer PCB, 4&#8243; \u00d7 5&#8243; footprint<\/li>\n\n\n\n<li>280 components (BGAs, QFNs, 0402 passives)<\/li>\n\n\n\n<li>Production volume: 2,000 boards\/year<\/li>\n\n\n\n<li>No test points in initial layout<\/li>\n<\/ul>\n\n\n\n<p><strong>The conversation:<\/strong> &#8220;We&#8217;ll use flying probe for testing. ICT fixtures are too expensive.&#8221;<\/p>\n\n\n\n<p><strong>Our analysis:<\/strong><\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Flying probe test time: 25 minutes per board<\/li>\n\n\n\n<li>Flying probe cost: $35 per board<\/li>\n\n\n\n<li>Annual testing cost: 2,000 \u00d7 $35 = $70,000<\/li>\n\n\n\n<li>ICT fixture cost: $6,500 (one-time)<\/li>\n\n\n\n<li>ICT test time: 75 seconds per board<\/li>\n\n\n\n<li>ICT cost per board: $2.00<\/li>\n\n\n\n<li>Annual ICT cost: 2,000 \u00d7 $2 = $4,000<\/li>\n<\/ul>\n\n\n\n<p><strong>Break-even:<\/strong> After 186 boards, ICT becomes cheaper. Over 5 years (10,000 boards), ICT saves $324,000.<\/p>\n\n\n\n<p><strong>Design changes we recommended:<\/strong><\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Add 120 bottom-side test points (40-mil diameter, 50-mil spacing)<\/li>\n\n\n\n<li>Test points on all power rails, IC power pins, and critical analog signals<\/li>\n\n\n\n<li>Grid-aligned placement on 100-mil centers<\/li>\n\n\n\n<li>ENIG surface finish on test points only (board used HASL)<\/li>\n<\/ul>\n\n\n\n<p><strong>Results:<\/strong><\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Design revision time: 8 hours<\/li>\n\n\n\n<li>Additional board cost: $0.75 per board (ENIG on test pads)<\/li>\n\n\n\n<li>ICT fault coverage: 92%<\/li>\n\n\n\n<li>First-pass yield improvement: 87% to 97%<\/li>\n\n\n\n<li>Defect detection before shipment: 98% (vs. 60% with visual inspection only)<\/li>\n<\/ul>\n\n\n\n<p><strong>ROI calculation:<\/strong><\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Year 1 testing cost savings: $64,000<\/li>\n\n\n\n<li>Reduced field failures: $12,000 saved (warranty claims avoided)<\/li>\n\n\n\n<li>Faster time to market: 2 weeks (no debugging of random field failures)<\/li>\n<\/ul>\n\n\n\n<p>The customer now designs every board with <strong>design for testability PCB<\/strong> principles from the start.<\/p>\n\n\n\n<h2 class=\"wp-block-heading\">Balancing DFT with Other Design Constraints<\/h2>\n\n\n\n<h3 class=\"wp-block-heading\">When Board Space Is Limited<\/h3>\n\n\n\n<p><strong>High-density designs face real conflicts between component placement and test points:<\/strong><\/p>\n\n\n\n<p><strong>Space-saving strategies:<\/strong><\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Via-in-pad test points (40-mil pad with filled 12-mil via)<\/li>\n\n\n\n<li>Test points on 50-mil grid instead of 100-mil (increases fixture cost but saves board space)<\/li>\n\n\n\n<li>Shared test points for electrically connected nets (reduce redundancy)<\/li>\n\n\n\n<li>Combine boundary scan and ICT (fewer physical test points)<\/li>\n<\/ul>\n\n\n\n<p><strong>Trade-off analysis:<\/strong><\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Adding 0.2 square inches for test points \u2192 $0.15 per board (fabrication cost)<\/li>\n\n\n\n<li>Skipping test points \u2192 $8-15 per board (flying probe cost)<\/li>\n\n\n\n<li>The math is clear unless board size drives enclosure cost<\/li>\n<\/ul>\n\n\n\n<h3 class=\"wp-block-heading\">DFT vs. Signal Integrity<\/h3>\n\n\n\n<p><strong>Test points add capacitance to high-speed signals:<\/strong><\/p>\n\n\n\n<p><strong>Typical test point capacitance:<\/strong><\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>40-mil pad: ~0.5 pF<\/li>\n\n\n\n<li>50-mil pad: ~0.8 pF<\/li>\n\n\n\n<li>Via-in-pad: ~0.3 pF (lower due to smaller pad)<\/li>\n<\/ul>\n\n\n\n<p><strong>Impact on signal integrity:<\/strong><\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Negligible for signals &lt;100 MHz<\/li>\n\n\n\n<li>Measurable for 500 MHz &#8211; 1 GHz (adds 5-10 ps delay)<\/li>\n\n\n\n<li>Problematic for multi-GHz signals (use boundary scan instead)<\/li>\n<\/ul>\n\n\n\n<p><strong>High-speed signal testing alternatives:<\/strong><\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Boundary scan for digital interconnects<\/li>\n\n\n\n<li>Embedded self-test (BIST) in FPGAs<\/li>\n\n\n\n<li>RF probe points (coplanar waveguide geometry)<\/li>\n\n\n\n<li>Functional test instead of ICT<\/li>\n<\/ul>\n\n\n\n<h3 class=\"wp-block-heading\">DFT in Safety-Critical Applications<\/h3>\n\n\n\n<p><strong>Aerospace and medical devices require higher test coverage:<\/strong><\/p>\n\n\n\n<p><strong>DO-254 (aerospace) and IEC 62304 (medical software) drive DFT requirements:<\/strong><\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Redundant test points on critical nets<\/li>\n\n\n\n<li>Test access to fail-safe circuits<\/li>\n\n\n\n<li>Verification of watchdog timers and safety monitors<\/li>\n\n\n\n<li>Documented test coverage analysis (% of nets tested)<\/li>\n<\/ul>\n\n\n\n<p><strong>Design for testability PCB in AS9100\/ISO 13485 environments:<\/strong><\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Test point redundancy: Two test points per critical net<\/li>\n\n\n\n<li>Test documentation: Formal test plans reviewed with design<\/li>\n\n\n\n<li>Traceability: Test point placement linked to FMEA analysis<\/li>\n\n\n\n<li>Fixture validation: Gauge R&amp;R studies on ICT fixtures<\/li>\n<\/ul>\n\n\n\n<p>We maintain separate DFT checklists for commercial vs. aerospace\/medical products. Safety-critical boards typically have 30-40% more test points and redundant access to critical signals.<\/p>\n\n\n\n<h2 class=\"wp-block-heading\">Partner With a CM That Understands Test Strategy<\/h2>\n\n\n\n<p>Design for testability isn&#8217;t just about placing test points &#8211; it&#8217;s about understanding your production volume, quality requirements, and cost constraints.<\/p>\n\n\n\n<p>Anzer USA provides DFT consultation as part of our NPI (New Product Introduction) process. Our test engineering team reviews designs at 50% layout completion and recommends:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Optimal test point count and placement<\/li>\n\n\n\n<li>ICT vs. flying probe cost analysis for your volume<\/li>\n\n\n\n<li>Fixture cost estimates before you commit to layout<\/li>\n\n\n\n<li>Test coverage analysis (percentage of nets accessible)<\/li>\n\n\n\n<li>Hybrid test strategies (ICT + boundary scan + functional)<\/li>\n<\/ul>\n\n\n\n<p>Our certifications (ISO 9001:2015, AS9100, ISO 13485) require documented test planning. We don&#8217;t quote a board without a test strategy discussion.<\/p>\n\n\n\n<p><strong>Your options:<\/strong><\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>ICT for production volumes >100 boards<\/li>\n\n\n\n<li>Flying probe for prototypes and low-volume builds<\/li>\n\n\n\n<li>Boundary scan for complex digital designs<\/li>\n\n\n\n<li>Functional test for mixed-signal and RF boards<\/li>\n\n\n\n<li>Hybrid approaches that balance cost and coverage<\/li>\n<\/ul>\n\n\n\n<p>Ready to optimize your next PCB for testability? <strong><a href=\"https:\/\/www.anzer-usa.com\/contact-us\">Contact Anzer USA<\/a><\/strong> to speak with a test engineer who can review your design and recommend the most cost-effective test strategy for your application.<\/p>\n\n\n\n<p><strong>On-Spec. On-Time. On-Budget.<\/strong> That includes catching defects before they reach your customers.<\/p>\n","protected":false},"excerpt":{"rendered":"<p>Key Takeaways What Is Design for Testability (And Why It Matters More Than Ever) Design for testability (DFT) is the practice of designing PCBs so manufacturing defects can be detected quickly, reliably, and cost-effectively. Your circuit might be perfect, but if you can&#8217;t verify that&#8230;<\/p>\n","protected":false},"author":8,"featured_media":3301,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"_jetpack_memberships_contains_paid_content":false,"footnotes":""},"categories":[170,169],"tags":[],"class_list":["post-3300","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-pcb-assembly","category-quality-assurance"],"jetpack_featured_media_url":"https:\/\/i0.wp.com\/www.anzer-usa.com\/resources\/wp-content\/uploads\/2026\/02\/a1e3d118-f5fd-41f4-8450-c81caaff62e6-scaled.webp?fit=2560%2C1429&ssl=1","jetpack_sharing_enabled":true,"_links":{"self":[{"href":"https:\/\/www.anzer-usa.com\/resources\/wp-json\/wp\/v2\/posts\/3300","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.anzer-usa.com\/resources\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/www.anzer-usa.com\/resources\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/www.anzer-usa.com\/resources\/wp-json\/wp\/v2\/users\/8"}],"replies":[{"embeddable":true,"href":"https:\/\/www.anzer-usa.com\/resources\/wp-json\/wp\/v2\/comments?post=3300"}],"version-history":[{"count":1,"href":"https:\/\/www.anzer-usa.com\/resources\/wp-json\/wp\/v2\/posts\/3300\/revisions"}],"predecessor-version":[{"id":3302,"href":"https:\/\/www.anzer-usa.com\/resources\/wp-json\/wp\/v2\/posts\/3300\/revisions\/3302"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/www.anzer-usa.com\/resources\/wp-json\/wp\/v2\/media\/3301"}],"wp:attachment":[{"href":"https:\/\/www.anzer-usa.com\/resources\/wp-json\/wp\/v2\/media?parent=3300"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/www.anzer-usa.com\/resources\/wp-json\/wp\/v2\/categories?post=3300"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/www.anzer-usa.com\/resources\/wp-json\/wp\/v2\/tags?post=3300"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}